For a long time, in order to achieve a higher chip density, a faster working speed and a lower power consumption, a feature size of a MOSFET (metal-oxide-semiconductor field effect transistor) is continuously scaled down according to Moore's law, and a working speed of the MOSFET is faster and faster. Currently, the feature size of the MOSFET has reached a nanometer level. However, a serious challenge is an emergence of a short-channel effect, such as a subthreshold voltage roll-off (Vt roll-off), a DIBL (drain-induced barrier lowering) and a source-drain punch through, thus increasing an off-state leakage current. Therefore, a performance of the MOSFET may be deteriorated. In addition, for an III-V compound device, there is a large lattice mismatch between III-V compound materials and Si materials, so that a dislocation density may be higher. Therefore, a buffer layer, for example, a GaAs layer, may need to be formed between the III-V compound materials and the Si materials, which may not only improve an interface state between the III-V compound materials and the Si materials, but also alleviate a lattice mismatch between the III-V compound materials and the Si materials. However, the conventional buffer layer is thick, and a defect density is high, thus further deteriorating the performance of the MOSFET.